A research team has implemented a novel method to achieve epitaxial growth of 1D metallic materials with a width of less than 1 nm. The group applied this process to develop a new structure for 2D semiconductor logic circuits. Notably, they used the 1D metals as a gate electrode of the ultra-miniaturized transistor.
A research team led by Director JO Moon-Ho of the Center for Van der Waals Quantum Solids within the Institute for Basic Science has implemented a novel method to achieve epitaxial growth of 1D metallic materials with a width of less than 1 nm. The group applied this process to develop a new structure for 2D semiconductor logic circuits. Notably, they used the 1D metals as a gate electrode of the ultra-miniaturized transistor.
The degree of integration in semiconductor devices is determined by the width and control efficiency of the gate electrode, which controls the flow of electrons in the transistor. In conventional semiconductor fabrication processes, reducing the gate length below a few nanometers is impossible due to the limitations of lithography resolution.
The International Roadmap for Devices and Systems by the IEEE predicts semiconductor node technology to reach around 0.5 nm by 2037, with transistor gate lengths of 12 nm. The research team demonstrated that the channel width modulated by the electric field applied from the 1D MTB gate can be as small as 3.9 nm, significantly exceeding the futuristic prediction.
Director JO Moon-Ho commented,"The 1D metallic phase achieved through epitaxial growth is a new material process that can be applied to ultra-miniaturized semiconductor processes. It is expected to become a key technology for developing various low-power, high-performance electronic devices in the future.
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